Programmable logic devices (PLDs) are a well-known type of integrated circuit that can be programmed (configured) to perform logic functions. Examples of such devices are complex programmable logic devices (CPLDs) and field programmable logic arrays (FPGAs), such as the ECP family of devices from Lattice Semiconductor Corporation. Programming a PLD is accomplished by loading a configuration bitstream that may include configuration data, addresses, and/or commands into the PLD. Configuration circuitry within the PLD then directs the configuration data into configuration memory in the PLD in accordance with the commands. The bitstream is typically provided to the PLD by an external tester/programmer or by another semiconductor device such as a CPU or nonvolatile memory such as flash memory or EEPROM.
It is not unusual for a system board to contain a number of PLDs and for these PLDs to be programmed from a single configuration bitstream. A common technique for configuring such PLDs is to daisy chain the devices so that they are programmed one after another sequentially. Examples of this technique are disclosed in U.S. Pat. Nos. 7,397,272 and 7,554,357, which are incorporated by reference herein in their entirety. Conventional daisy chaining techniques, however, have a number of disadvantages. One drawback is that they do not work with PLDs that receive their bitstreams through serial peripheral interface (SPI) ports (i.e., interfaces). SPI is an industry standard protocol that is widely used in embedded systems for interfacing microprocessors and various devices such as sensors, memory chips and multimedia cards. See, for example, U.S. Pat. No. 7,570,078, which is incorporated by reference herein in its entirety. The SPI protocol, however, does not support daisy chaining slave SPI devices to one master SPI device, such as a CPU. Another drawback is that conventional daisy chaining techniques do not typically permit the PLDs in the chain to be configured or reconfigured in different sequences.
Alternative techniques to daisy chaining exist for programming multiple PLDs through their SPI ports using a single bitstream, although they also have disadvantages. One technique is to connect each PLD to a unique SPI port of the CPU. But this approach limits the number of connected PLDs to the number of SPI ports available on the CPU. Another technique is to connect the SPI port of the CPU to the SPI ports of multiple PLDs, with a demultiplexer inserted between the chip select pin of the CPU's SPI port and the chip select pins of each of the PLD's SPI ports. A general purpose IO signal from the CPU then controls the demultiplexer, allowing the CPU to individually select the PLDs for configuration. But this approach requires adding a demultiplexer to the system board, which increases the board's cost.
Accordingly, a need remains for a better technique for configuring multiple PLDS through their SPI ports from a single configuration source.